1) Field of the Invention
This invention pertains to the field of semiconductor memory devices, and more particularly, to a Dynamic Random Access Memory (DRAM) cell produced of semiconductor transistor structures common to semiconductor logic devices.
2) Background of the Related Art
Semiconductor memory devices may be largely divided into Read Only Memories (ROMs) and Random Access Memories (RAMs), such as Dynamic RAMs (DRAMs) and Static RAMs (SRAMs). RAMs, also referred to as volatile memories because the stored data is destroyed with the passage of time upon removal of the power supply, allow rapid data storage and data retrieval.
Although they must be refreshed, DRAMs generally allow a higher integration density than SRAMs, which have more transistors and generally occupy more area.
FIG. 1 shows a circuit diagram for a DRAM device 100. A word line 110 is connected to a gate 115 of a transistor 120. The transistor has a source 125 connected with a bit line 130 and a drain 135 connected with one side of a capacitor 140. The other side of the capacitor 140 is connected with a fixed potential 175.
The transistor 120 may be, for example, a PMOS transistor. In that case, the fixed potential 175 is ground potential. To program the DRAM device 100 with a potential V.sub.DD, the word line 110 is connected with the ground potential and the bit line 130 is connected with the power supply potential, V.sub.DD. To read the DRAM device, the word line 110 is connected with the ground potential and the bit line voltage is sensed.
Alternatively, the transistor 120 may be an NMOS transistor. In that case, the fixed potential 175 is a supply potential V.sub.DD. To program the DRAM device 100 with the ground potential, the word line 110 is connected with the supply potential V.sub.DD and the bit line 130 is connected with the ground potential. To read the DRAM device, the word line 110 is connected with the supply potential V.sub.DD and the bit line voltage is sensed.
A number of different memory cell structures have been used for a DRAM device. Generally, design goals include producing a DRAM cell which occupies a small area (to facilitate high scale integration) and providing an adequate capacitance to allow the memory refresh rate to be lower.
FIG. 2 shows one configuration of a stacked capacitor DRAM 200 according to the prior art. First and second impurity regions 225 and 235 are formed in a top surface of the semiconductor substrate 205. A bit line 230 is formed and connected to the first impurity region 225. A word line is connected to a gate electrode 215 arranged above and between the first and second impurity regions. The second impurity region 235 is connected with a stacked capacitor 240, comprised of a first electrode 242 a dielectric layer 244 and a second electrode 246. The capacitor 240 is stacked on top of the second impurity region 235.
FIG. 3 shows one configuration of a trench capacitor DRAM 300 according to the prior art. First and second impurity regions 325 and 335 are formed in a top surface of the semiconductor substrate 305. A bit line 330 is formed and connected to the first impurity region 325. A word line is connected to a gate electrode 315 arranged above and between the first and second impurity regions. The second impurity region 335 is connected with a stacked capacitor 340, comprised of a first electrode 342 a dielectric layer 344 and a second electrode 346. The capacitor 340 is formed in a trench cut into the semiconductor substrate at the second impurity region.
Disadvantageously, these prior art DRAM memory cell structures are not readily adaptable to integration in a logic device such as a gate array.
For instance, a CMOS gate array device typically comprises pairs of NMOS and PMOS transistors. In turn each transistor pair comprises an NMOS transistor formed in a P-well and a PMOS transistor formed in an N-well, where the wells are separated by field oxide regions. Processes used to produce the trench capacitor or stack capacitor are typically not performed in the production of such a CMOS gate array device. Yet, it is desirable to provide dynamic random access memory cells in a gate array device.
Accordingly, it would be advantageous to provide a DRAM cell which may be easily integrated into a semiconductor logic device. It would also be advantageous to provide a DRAM cell which may be easily integrated into a gate array logic device. It would be further advantageous to provide a DRAM cell which can use the same process technologies and array structures which are used to manufacture gate array logic circuitry. Other and further objects and advantages will appear hereinafter.